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LC72711W, 72711lw no.6167-1/26 overview the LC72711W and lc72711lw are data demodulator ics for receiving fm multiplex broadcasts for mobile reception in the darc format. this ic includes an onchip bandpass filter for extracting the darc signal from the fm baseband signal. furthermore, since this ic supports all of the it-r recommended fm multiplex frame structures (methods a, a? b, and c), it is optimal for worldwide market radios that provide fm multiplex reception. the LC72711W and lc72711lw support both parallel and ccb serial cpu interfaces. functions ? adjustment-free 76khz scf bandpass filter ? supports all fm multiplex frame structures (methods a, a? b, and c) under cpu control. ? msk delay detection system based on a 1t delay. ? error correction function based on a 2t delay (in the msk detection stage) ? digital pll based clock regeneration function ? shift-register 1t and 2t delay circuits ? block and frame synchronization detection circuits ? functions for setting the number of allowable bic errors and the number of synchronization protection operations. ? error correction using (272, 190) codes ? built-in layer 4 crc code checking circuit ? on-chip frame memory and memory control circuit for vertical correction ? 7.2mhz crystal oscillator circuit ? two power saving modes: stnby and ec stop ? applications can use either a parallel cpu interface (dma) or a ccb serial interface. ? supply voltage: 4.5 to 5.5v (LC72711W), 2.7 to 3.6v (lc72711lw) sanyo semiconductors data sheet o0307hkim 20070822-s00004, 20070821-s00010 / 12100rm (ot) specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. LC72711W, lc72711lw cmos ic mobile fm multiplex broadcast (darc) receiver ic ordering number : en6167a ? ccb is a trademark of sanyo electric co., ltd. ? ccb is sanyo? original bus format and all the bus addresses are controlled by sanyo. http://www.sanyosemi.com/en/network/
LC72711W, 72711lw no.6167-2/26 specifications absolute maximum ratings at ta=25 c, v ss =0v. items in parentheses refer to the lc72711lw. parameter symbol conditions ratings unit maximum supply voltage v dd (-0.3 to +5.5) -0.3 to +7.0 v input voltage v in 1 a0/cl, a1/ce, a2/di, rst, stnby -0.3 to +7.0 v v in 2 pins other than v in 1 -0.3 to v dd +0.3 v output voltage v out 1 do -0.3 to +7.0 v v out 2 pins other than v out 1 -0.3 to v dd +0.3 v output current i out 1 int, rdy, dreq, and d0 to d15 0 to 4.0 ma i out 2 pins other than i out 1 0 to 2.0 ma allowable output current (total) i ttl total for all the output pins 20 ma allowable power dissipation pd max ta at ta=-40 to +85 c, v ss =0v ratings parameter symbol conditions min typ max unit supply voltage v dd 4.5 5.5 v high-level input voltage v ih 1 a0/cl, a1/ce, a2/di, rst, stnby 0.7v dd 5.5 v v ih 2 dack, wr, rd, cs, sp, buswd, a3, iocnt1, iocnt2 0.7v dd v dd v low-level input voltage v il 1 pins for which v ih 1 applies v ss 0.3v dd v v il 2 pins for which v ih 2 applies v ss 0.3v dd v oscillator frequency f osc this ic operates with a frequency precision of 250 ppm 7.2 mhz xin input sensitivity v xi with a sine wave input to xin, capacitor coupling, 400 1500 mvrms v dd =+4.5 to +5.5v input amplitude v mpx with a 100% modulated composite signal input to 150 400 mvrms mpxin, v dd =+4.5 to +5.5v [serial i/o] clock low-level period t cl a0/cl 0.7 s clock high-level period t ch a0/cl 0.7 s data setup time t su a0/cl, a2/di 0.7 s data hold time t hd a0/cl, a2/di 0.7 s ce wait time t el a0/cl, a1/ce 0.7 s ce setup time t es a0/cl, a1/ce 0.7 s ce hold time t eh a0/cl, a1/ce 0.7 s data latch change time t lc a1/ce 0.7 s data output time t ddo do, a0/cl 277 555 ns crc4 change time t crc crc4, a0/cl 0.7 s [LC72711W] allowable operating ranges: parallel interface at ta=-40 to +85 c, v ss =0v ratings parameter symbol conditions min typ max unit [parallel i/o] address to rd setup t sard a0/cl, a1/ce, a2/di, a3, rd 20 ns rd to address hold t hard a0/cl, a1/ce, a2/di, a3, rd, t wrdl =>250ns -20 ns rd low-level width t wrdl 1 rd 250 ns rd low-level width (when rdy is used) t wrdl 2 rd 100 ns rd cycle wait t cyrd a0/cl, a1/ce, a2/di, a3, rd 150 ns rdy width (register read) t wrdy rdy 60 210 ns rd data hold t rdh rd, datn 0 ns address to wr setup t sawr a0/cl, a1/ce, a2/di, a3, wr 20 ns wr to address hold t hawr a0/cl, a1/ce, a2/di, a3, wr 20 ns wr cycle wait t cywr a0/cl, a1/ce, a2/di, a3, wr 150 ns wr low-level width t wwrl wr 200 ns wr data hold t wdh wr, datn 0 ns rdy output delay t drdy rd, rdy 0 30 ns corrected output rd width t wdrd 1 rd (buswd=l 8bits) 300 ns rd (buswd=h 16bits) 540 ns corrected output rd width t wdrd 2 rd (buswd=l 8bits) 100 ns (when rdy is used) rd (buswd=h 16bits) 300 ns continued on next page.
LC72711W, 72711lw no.6167-3/26 continued from preceding page. ratings parameter symbol conditions min typ max unit rdy width (corrected output read) t wdrdy rdy (buswd=l 8bits) 60 210 ns rdy ((buswd=h 16bits) 300 490 ns dack to dreq delay t dreq dreq, dack 260 ns dma cycle wait t cydm rd, dreq 420 ns rd low-level width (dma) t wrdm rd 300 ns notes: application designs must take the rdy signal output delay into consideration if the rdy signal is used as the cpu bus wa it signal. if the rdy signal is not used, (that is, if no wait states are inserted) the value of the rd low-level width will be 250ns (min imum). [lc72711lw] allowable operating ranges at ta=-40 to +85 c, v ss =0v ratings parameter symbol conditions min typ max unit supply voltage v dd 2.7 3.6 v high-level input voltage v ih 1 a0/cl, a1/ce, a2/di, rst, stnby 0.7v dd 5.5 v v ih 2 dack, wr, rd, cs, sp, buswd, a3, iocnt1, iocnt2 0.7v dd v dd v low-level input voltage v il 1 pins for which v ih 1 applies v ss 0.3v dd v v il 2 pins for which v ih 2 applies v ss 0.3v dd v oscillator frequency f osc this ic operates with a frequency precision of 250 ppm 7.2 mhz xin input sensitivity v xi with a sine wave input to xin, capacitor coupling, 400 900 mvrms v dd =+2.7 to +3.6v v mpx 1 with a 100% modulated composite signal input to 120 350 mvrms input amplitude mpxin, v dd =+3.3v v mpx 2 with a 100% modulated composite signal input to 120 180 mvrms mpxin, v dd =+2.7v [serial i/o] clock low-level period t cl a0/cl 0.7 s clock high-level period t ch a0/cl 0.7 s data setup time t su a0/cl, a2/di 0.7 s data hold time t hd a0/cl, a2/di 0.7 s ce wait time t el a0/cl, a1/ce 0.7 s ce setup time t es a0/cl, a1/ce 0.7 s ce hold time t eh a0/cl, a1/ce 0.7 s data latch change time t lc a1/ce 0.7 s data output time t ddo do, a0/cl 277 555 ns crc4 change time t crc crc4, a0/cl 0.7 s [lc72711lw] allowable operating ranges: parallel interface at ta=-40 to +85 c, v ss =0v ratings parameter symbol conditions min typ max unit [parallel i/o] address to rd setup t sard a0/cl, a1/ce, a2/di, a3, rd 20 ns rd to address hold t hard a0/cl, a1/ce, a2/di, a3, rd, t wrdl =>250ns -20 ns rd low-level width t wrdl 1 rd 280 ns rd low-level width (when rdy is used) t wrdl 2 rd 100 ns rd cycle wait t cyrd a0/cl, a1/ce, a2/di, a3, rd 150 ns rdy width (register read) t wrdy rdy 60 230 ns rd data hold t rdh rd, datn 0 ns address to wr setup t sawr a0/cl, a1/ce, a2/di, a3, wr 20 ns wr to address hold t hawr a0/cl, a1/ce, a2/di, a3, wr 20 ns wr cycle wait t cywr a0/cl, a1/ce, a2/di, a3, wr 150 ns wr low-level width t wwrl wr 200 ns wr data hold t wdh wr, datn 0 ns rdy output delay t drdy rd, rdy 0 50 ns corrected output rd width t wdrd 1 rd (buswd=l 8bits) 300 ns rd (buswd=h 16bits) 540 ns corrected output rd width t wdrd 2 rd (buswd=l 8bits) 100 ns (when rdy is used) rd (buswd=h 16bits) 300 ns rdy width (corrected output read) t wdrdy rdy (buswd=l 8bits) 60 230 ns rdy ((buswd=h 16bits) 300 490 ns dack to dreq delay t dreq dreq, dack 260 ns continued on next page.
LC72711W, 72711lw no.6167-4/26 continued from preceding page. ratings parameter symbol conditions min typ max unit dma cycle wait t cydm rd, dreq 420 ns rd low-level width (dma) t wrdm rd 300 ns notes: application designs must take the rdy signal output delay into consideration if the rdy signal is used as the cpu bus wa it signal. if the rdy signal is not used, (that is, if no wait states are inserted) the value of the rd low-level width will be 280ns (min imum). [LC72711W] electrical characteristics at v dd =+4.5 to +5.5v, within the allowable operating ranges ratings parameter symbol conditions min typ max unit v oh 1 i o =2ma, bck, fck, block, flock, v dd -0.4 v high-level output voltage crc4, clk16, data v oh 2i o =4ma, int, rdy, dreq, d0 to d15 v dd -0.4 v v ol 1i o =2ma, pins for which v oh 1 applies 0.4 v low-level output voltage v ol 2i o =4ma, pins for which v oh 2 applies 0.4 v v ol 3i o =2ma, do, int 0.4 v i ih 1 v in =5.5v, a0/cl, a1/ce, a2/di, rst, 1.0 a high-level input current stnby i ih 2v in =v dd d, all input pins other than i ih 1 1.0 a low-level input current i il v in =v ss d, all input pins -1.0 a input resistance r mpx mpxin -vssa f=100khz 50 k ? ? at v dd =+2.7 to +3.6v, within the allowable operating ranges ratings parameter symbol conditions min typ max unit v oh 1 i o =1ma, bck, fck, block, flock, v dd -0.4 v high-level output voltage crc4, clk16, data v oh 2i o =2ma, int, rdy, dreq, d0 to d15 v dd -0.4 v v ol 1i o =1ma, pins for which v oh 1 applies 0.4 v low-level output voltage v ol 2i o =2ma, pins for which v oh 2 applies 0.4 v v ol 3i o =1ma, do, int 0.4 v i ih 1 v in =5.5v, a0/cl, a1/ce, a2/di, rst, 1.0 a high-level input current stnby i ih 2v in =v dd d, all input pins other than i ih 1 1.0 a low-level input current i il v in =v ss d, all input pins -1.0 a input resistance r mpx mpxin -vssa f=100khz 50 k ?
LC72711W, 72711lw no.6167-5/26 continued from preceding page. ratings parameter symbol conditions min typ max unit hysteresis voltage v hys a0/cl, a1/ce, a2/di, a3, cs, rd, wr, 0.1v dd dv dack, iocnt1, iocnt2, rst, stnby internal feedback resistor rf xin, xout 1.0 m ? 10.0 10.0 12.0 12.0 0.15 0.5 (1.5) 0.1 1.7max 0.18 0.5 (1.25) 116 17 32 33 48 49 64 sanyo : sqfp64(10x10) iocnt1 wr rd a0/cl a1/ce a2/di a3 cs stnby buswd sp rst 32 d15 49 d14 d13 tin vssa d12 vref mpxin d11 d10 vdda d9 flout d8 nc nc cin d7 d6 tpc1 64 1 16 d5 tpc2 bck crc4 fck block flock data clk16 iocnt2 vddd xout int vddd vssd do nc test tosel1 tosel2 vssd xin vddd rdy vssd dack dreq d4 d3 d2 d1 d0 LC72711W, lc72711lw (top view)
LC72711W, 72711lw no.6167-6/26 block diagram pin functions pin no. pin function i/o pin circuit 3 iocnt1 data bus i/o control 1 (sp=low)*1 4 iocnt2 data bus i/o control 2 (sp=low)*1 13 dack dma acknowledge (sp=low)*1 38 wr write control signal (sp=low)*1 39 rd read control signal (sp=low)*1 40 a0/cl address input 0 (sp=low) ccb cl input (sp=high) input 41 a1/ce 1 (sp=low) ccb ce input (sp=high) 42 a2/di 2 (sp=low) ccb di input (sp=high) 43 a3 3 (sp=low)*1 44 cs chip select input (sp=l)*1 46 rst system reset input (negative logic) 45 stnby standby mode (positive logic) 47 sp sp=low: parallel, sp=high: serial 48 buswd buswd=low: 8 bits, buswd=high: 16bits 60 test the test pin must be connected to the digital system ground (v ss ). 58 tpc1 must be connected to the digital system power supply (v dd ) or ground input (v ss ) in normal operation. 59 tpc2 as above 61 tosel1 as above 62 tosel2 as above 49 tin as above 5 clk16 clock regeneration monitor 6 data demodulated data monitor 9 fck frame start signal output 10 bck block start signal output 7 flock outputs a high level during frame synchronization output 8 block outputs a high level during block synchronization 11 crc4 level 4 crc detection result output 33 int external cpu interrupt request output 12 dreq dma request signal 16 rdy read ready signal continued on next page. lpf mpxin 7.2mhz vref xin vssa vdda xout rst clk16 data bck fck flock block stnby vssd vddd lpf 76khz bpf (scf) vref iocnt1 dack dreq iocnt2 crc4 flout cin vref cs rd wr rdy int buswd tin sp a3 do a2/di a1/ce a0/cl d0 to d15 pn decoding memory array data address error correction: layer 2 crc anti-aliasing filter timing control synchronization regeneration msk correction circuit clock regeneration 2t delay 1t delay output control (cpu interface) and layer 4 crc detection circuit
LC72711W, 72711lw no.6167-7/26 continued from preceding page. pin no. pin function i/o pin circuit data bus 17 to 24 d0 to d7 the bus width can be set to be either 8 bits or 16bits by the buswd i/o pin (pin 48). for data input, only the lower 8 bits (d0 to d7) are valid. 25 to 32 d8 to d15 data bus (in 16-bit mode) output these pins are held in the output off state when buswd is low. 64 xin connections for the system clock crystal oscillator circuit. i/o 1 xout the xin pin can also be used as an external clock signal input. 53 mpxin baseband (multiplex) signal input input 55 flout subcarrier output (76khz bandpass filter output) output 56 cin subcarrier input (comparator input) input 52 vref reference voltage output (vdda/2) output 36 do ccb serial interface data output output 37 50 nc this pin must be left open 57 54 v dd a analog system power supply - 51 v ss a analog system ground - 2, 15, 34 v dd d digital system power supply (+2.7v to +5.5v) - 14, 35, 63 v ss d digital system ground - notes: 1. this pin must be connected to v dd d or v ss d if the ic is used in serial interface mode (when sp is high). 2. a capacitor of at least 2000pf must be inserted between v dd d and v ss d. control registers this ic includes both registers that can be read and registers that can be written. these registers can be accessed using either the serial interface (ccb) or the parallel interface. the sp pin switches between these interfaces. the initial values of the write registers are the data loaded into internal registers when a reset signal (rst) is received. these values are recommended values that do not need to be changed during normal operation. if the parallel interface is used, applications must hold the address fixed at 00h when reading out data to which error correction has been applied. if the ccb interface is used, the application needs only to specify the ccb address (#fb). the address 00h is an invalid address for writing. the addresses other than those specified below are control addresses particular to the ic. applications must not specify those addresses. continued on next page. -- + vref -- + vssa vdda
LC72711W, 72711lw no.6167-8/26 continued from preceding page. address register function r/w address register function r/w 1 bic number of allowable bic errors w 1 stat status register r 2 syncb block synchronization: error protection count w 2 blno block number register r 3 syncf frame synchronization: error protection count w 4 ctl1 control register 1 w 5 ctl2 control register 2 w 6 crc4 layer 4 crc register w number of allowable bic errors address register r/w initial value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01h bic w 22h back protection (lsb) forward protection (lsb) the synchronization circuit in this ic operates by recognizing a 16-bit bic code. the number of allowable errors is the number of incorrect bits allowed in those 16 bits. this data sets up separate values for forward protection mode (when synchronized) and for back protection mode (when not synchronized). the default value is to allow 2 incorrect bits in both forward and back modes. if the block synchronization discrimination output (block) is used for discriminating whether or not fm multiplex data is present, we recommend setting the back protection mode bic allowable error count to 1 or 0. block synchronization: error protection count address register r/w initial value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 02h syncb w 17h back protection (lsb) forward protection (lsb) the synchronization protection count can be set separately for both forward and back protection. the count conditions for the protection counts are as follows. ? back protection mode (not synchronized: block=low) if the timing of the ic internal synchronization free-running counter matches the timing of the received bic, the protection count is incremented by 1. contrarily, if the timings of the ic internal counter and the received bic do not match, the protection counter is cleared to 0. the timing of the count is the timing of the ic internal counter. ? forward protection mode (synchronized: block=high) in reverse to the back protection mode, if the timing of the ic internal free-running counter does not match the detection timing of the received bic, the protection counter is incremented, and if the timings match, the protection counter is cleared to 0. figure 1 shows the states of the protection counter for the cases where the forward and back protection counts are both 3. this ic defines the value of the protection counter to be 1 at the point that a match or a discrepancy occures between the ic internal timing and the timing of the received bic occurs. for example, when the value of the back protection count is 2, the ic internal timing and the timing of the received bic will have matched two times consecutively. if the protection data is set to new values, for example if the protection counts are set to 3 as assumed in figure 1, applications must send values which are 1 less than the intended value; in this case 22h. similarly, if the value is set to 00h, the protection counts will, by definition, be set to 1 for both the forward and back directions. however, note that the resulting operation will be equivalent to there being no protection circuit. the default values are 8 for the forward protection count and 2 for the back protection count. if the block synchronization output (block) is used for discriminating whether or not fm multiplex data is present, we recommend setting the block synchronization back protection count to a value that is more strict than the default value. (that is, we recommend replacing the default value of 2 with a value of 3 or higher.) figure 1 block synchronization protection operation (forward
LC72711W, 72711lw no.6167-9/26 frame synchronization: error protection count address register r/w initial value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 03h syncf w 17h back protection (lsb) forward protection (lsb) this ic detects the bic characteristic inflection points which occur at four places in a single frame, and increments or decrements a protection counter depending on whether or not they match the ic internal frame synchronization timing counter. as is the case with the block synchronization error protection value, applications must set these to values one less than the desired protection count. the default values are 8 for the frame synchronization forward protection count and 2 for the back protection count. control register 1 address register r/w initial value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 04h ctl1 w 00h crc4_rst do_move int_move sync_rst ec_stop vec_halt rtib frame ? frame 0: specifies method b. (default) 1: specifies method a. ? rtib 0: real-time information blocks present. (default) 1: no real-time information blocks. in the itu-r recommended frame structure method a, a total of 12 data blocks can be inserted in the parity data area (the area that consists of 82 consecutive blocks of parity packets). if this ic is used in a system that has no real- time information blocks (rtib), this flag must be set. note that if this flag is changed, frame synchronization is retained in the synchronized state for the time corresponding to the forward protection count, and then switches to the unsynchronized state. to quickly reestablish frame synchronization, applications must reset the synchronization circuit using the sync_rst flag. ? vec_halt 0: vertical correction and the second horizontal correction processing are performed. (default) 1: vertical correction and the second horizontal correction processing are not performed. all ic operations related to vertical correction and the second horizontal correction are stopped by setting this flag. note that in data output, only data to which the first horizontal correction has been applied will be output. ? ec_stop 0: all functions operate. (default) 1: only the msk detection circuit and the synchronization regeneration circuit operate. this flag stops all operations relating to error correction (including ram access), data output, and other operations. while all ic operations are stopped in standby mode, msk demodulation, the synchronization circuit, the serial data input circuit, and the layer 4 crc circuit continue to operate in this mode. ? sync_rst 0: (default) 1: resets just the synchronization regeneration circuit. clears the synchronization status and the synchronization protection status in the synchronization circuit block, and sets the circuit to the unsynchronized state. this allows the circuit to quickly pull in to frame synchronization when the frame synchronization is incorrect for the new reception data following tuning, when the radio has been tuned to a new station. while this flag is used for synchronization related sections of the system, it does not initialize the registers that set the number of allowable bic errors, the block synchronization forward and back protection counts, and the frame synchronization forward and back protection counts. also note that during a synchronization block reset, the int signal is not output and the do pin outputs a high level (high-impedance). this flag is not automatically reset to 0. applications must send a 0 value after setting this flag. ? int_move 0: data is only output when error correction has completed, layer 2 crc has completed, and the data was received with the circuit synchronized. (default) 1: all data is output. (operation is identical to that of the lc72700e.) in the default state, this ic only outputs data that has been fully error corrected and that was received in both block and frame synchronization. (this also includes the layer 2 crc check.) to acquire all data as provided by the lc72700, applications must set both this flag and the vec_out (bit2) flag in control register 2 as described below.
LC72711W, 72711lw no.6167-10/26 ? do_move (valid only when sp is high.) 0: the high state (high impedance) is held at all times other than when data is being output. (default) 1: operate identically to the lc72700 when changes are linked to the int signal, i.e. when both int_move and vec_out are set to 1. ? crc4_rst 0: (default) 1: reset the layer 4 crc detection circuit. this flag is not automatically reset to 0. applications must send a 0 value after setting this flag. control register 2 address register r/w initial value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 05h ctl2 w 00h subblk blk_rst dack dreq rdy vec_out dma_rd dma ? dma (valid only when sp is low.) 0: do not use dma transfer for readout of post-error correction data. (default) 1: use dma transfer for readout of post-error correction data. ? dma_rd (valid only when sp is low.) 0: use the rd signal as the dma transfer read control signal. (default) 1: use the dack signal as the dma transfer read control signal. ? vec_out 0: do not perform post-horizontal correction output when vertical correction processing is not performed. (default) 1: output all data, even when vertical correction processing is not performed. (operation identical to that of the lc72700e) when this flag is set and a frame of data with absolutely no errors is received, data that is completely identical to the corresponding post-horizontal correction data is output with the timing of the output of post-vertical correction data, even if vertical correction is not performed. this flag must be set to create interface specifications identical to those of the lc72700. ? rdy (valid only when sp is low.) 0: the rdy output is issued with timing 1. (default) 1: the rdy output is issued with timing 2. ? dreq (valid only when sp is low.) 0: negative logic is used for the polarity of the dreq signal. (default) 1: positive logic is used for the polarity of the dreq signal. ? dack (valid only when sp is low.) 0: negative logic is used for the polarity of the dack signal. (default) 1: positive logic is used for the polarity of the dack signal. ? blk_rst 0: (default) 1: resets the block synchronization circuit only. sets the block synchronization status to unsynchronized and clears the block synchronization protection counter. however, note that this has no effect on the frame synchronization functions. also note that during a synchronization block reset, the int signal is not output and the do pin outputs a high level (high-impedance). this flag is not automatically reset to 0. applications must send a 0 value after setting this flag. ? subblk 0: normal status. (default) 1: set to 1 when a substation is temporarily received. rdy signal output timing rd rdy timing1 rdy timing2 datn valid output
LC72711W, 72711lw no.6167-11/26 layer 4 crc register address register r/w initial value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 06h crc4 w 00h (lsb) this is the data group write register used for the layer 4 crc check. it is used only when the parallel interface is used. applications should specify the dedicated ccb address when using the serial interface. status register address register r/w initial value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 01h stat r - vh blk frm err pri head crc4 rtib ? vh 0: indicates data for which only horizontal correction was performed. 1: indicates data for which after horizontal correction, vertical and then second horizontal correction were performed as well. packet data with an rtib flag is output with vh set to 0. ? blk 0: indicates data that was received with block synchronization unsynchronized. 1: indicates data that was received with block synchronization synchronized. ? frm 0: indicates data that was received with frame synchronization unsynchronized. 1: indicates data that was received with frame synchronization synchronized. ? err 0: indicates data for which error correction completed and no errors were detected in the level 2 crc check. 1: indicates data for which error correction was not possible or for which errors were detected in the level 2 crc check. ? pri 0: indicates data that was inferred to be data block data by the frame synchronization circuit. 1: indicates data that was inferred to be parity block data by the frame synchronization circuit. packet data with an rtib flag is output with pri set to 0. ? head 0: 1: indicates data that was inferred to be in the frame head block by the frame synchronization circuit. this flag is valid only when vh is 0. ? crc4 0: indicates that the layer 4 crc detection circuit division registers were not all zeros. 1: indicates that the layer 4 crc detection circuit division registers were all zeros, i.e. that there were no errors. the result at the point immediately prior to register readout is loaded into this flag. ? rtib 0: 1: indicates the data is a real-time information block. (this bit is valid only in method a?.) this bit is fixed at 0 during method a and method b reception. block number register address register r/w initial value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 02h blno r - bln7 bln6 bln5 bln4 bln3 bln2 bln1 bln0 indicates the block number or the parity block number of the output data. a single frame consists of data blocks numbered 0 to 189 and parity blocks numbered 0 to 81. output following vertical correction does not include parity block data. the value of the block number register is undefined if vec_halt (bit 2 in control register 1) is set to 1.
LC72711W, 72711lw no.6167-12/26 data update timing for read registers the data in the two read registers (the status register at address 01h and the block number register at address 02h) is updated in the 1 ms interval between 1 ms prior to the output of the interrupt control signal (int) and a point immediately before the int output. in normal processing, when an interrupt occurs, the application will first determine the nature of the data packet that will be output by the current interrupt signal by reading out the status register, and determine if it is necessary to read out that data. for example, if error correction failed and the erroneous data is not required, the application should simply wait for the next interrupt. if the ccb interface is used, the application reads out the data from ccb address #fb, and determines the status from the additional 16 bits of data. it then either reads out the following data or sets the ce signal low to cancel the readout. applications can also read out data asynchronously with respect to the interrupt signal. in this case, the application checks the current reception status by reading out the status register and checking bit 6 (data received in the block synchronized state) and bit 5 (data received in the frame synchronized state). in this case, using data for which bit 7 (vh) is 0 provides superior real time characteristics. cpu interface timing ? register read timing * t hard stipulates the earliest timing for a0 to a3 and cs. cs rd rdy a0 to a3 t sard t drdy t wrdy t wrdl 1, t wrdl 2 t cyrd t hard t rdh valid output datn
LC72711W, 72711lw no.6167-13/26 ? register write timing ? post-correction data read timing cs wr cs rd a0 to a3 datn t sawr t wwrl t cywr t hawr t wdh a0 to a3 rdy datn t sard t wdrd 1, t wdrd 2t cyrd t wdrdy valid output valid output t rdh t drdy *: a0 to a3: when post-correction data is read, a0 to a3 will be held fixed at 0.
LC72711W, 72711lw no.6167-14/26 ? post-correction data read timing (dma) layer 4 crc detection circuit this function provides data group error detection, i.e. layer 4 crc. when the stipulated number of bytes of data group data and the crc detection word (16 bits) are written to the layer 4 crc register (address 6), if either the crc4 pin outputs a high level or the crc4 flag (bit 1 in the status register at address 1) is set to 1 then there were no errors in the data. the crc4 pin or crc4 flag in the status register outputs a high level if the ic internal crc detection register bits are all in the logic 0 state. when this function is used to perform a layer 4 crc check, applications must initialize the ic internal crc detection register before transferring the data for a single data group. this initialization is performed by sending data for bit 7 (crc4_rst) in control register 1. note that since this initialization flag is not automatically reset to 0, after the application sets this flag it must then send another data item that resets it to 0 before sending the layer 4 crc check data. if there were no errors in all the received data groups, the crc register will, necessarily, be all zeros after the crc check for a given data group. therefore, as long as there are no errors detected in the layer 4 crc check, the application does not need to initialize the crc detection register again using the control register as described above. there is no upper limit on the total data length of data groups that can be transferred. also, when the serial interface issued, the ccb transfers can be divided into multiple transfer operations. the generating polynomial g(x) for the crc code is as follows. g (x) = x 16 + x 12 + x 5 + 1 structure of the post-correction output data the total length of the prepared output data is always 176 bits, i.e. 22 bytes. the layer 2 crc data (14 bits) and the parity data (82 bits) are not output. the data in each packet in the post-correction data is output in order starting at the beginning in 8- or 16-bit units. bic codes are not output. when the cpu reads out the data, it can easily select the data by checking the status register first. the cpu can then simply ignore data determined to be unnecessary without having to read it out by simply waiting until the next interrupt arrives. data block (176bits) post-error correction data layer 2 crc (14bits) parity (82bits) *: this data is not output. structure of a single data packet (total length: 272bits. bic is not included.) cs rd a0 to a3 datn dack dreq t dreq t rdh t cydm t wrdm *: a0 to a3: when post-correction data is read, a0 to a3 will be held fixed at 0. *: dreq and dack: the polarity of these signals can be set. *: applications can select whether the dr or dack signal is used for readout.
LC72711W, 72711lw no.6167-15/26 cpu interface ccb format data is input and output using the ccb (computer control bus) format, which is sanyo?s audio ic serial bus format. this ic uses an 8-bit address ccb with the address shown below. the ccb address is sent while ce is low, and the ccb i/o mode is determined when ce is set high. i/o mode ccb address item b0 b1 b2 b3 a0 a1 a2 a3 input 0 1 0 1 1 1 1 1 16-bit control data input output 1 1 0 1 1 1 1 1 data corresponding to the number of clock (cl) cycles is output input 0 0 1 1 1 1 1 1 data input mode for the layer 4 crc detection circuit (8-bit units) output 1 0 1 1 1 1 1 1 register output only data input (register write) data is stored in an ic internal register. the ccb address #fa and 16 bits of data (di0 to di15) are input to the di pin. the bits are assigned as follows. although di12 to di15 are unused data, arbitrary values must be provided to complete a full 16 bits of data. see the control register section earlier in this document for details on the register contents and addresses. details on writing to the layer 4 crc check register are described later in this document. (the ccb address #fc is used for this function.) di0 di1 di2 di3 di4 di5 di6 di7 di8 di9 di10 di11 di12 to di15 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 unused data (lsb) input data (8 bits) (msb) register address data output (post-correction data output) the ic outputs packet data to which error correction processing has be applied. the application inputs the ccb address #fb to di. *: the do pin is normally left open. since the do pin is an n-channel open-drain output, the data change time from a low-level output to a high-level output differs due to the pull-up resistor. internal data latch operation a3 di15 di14 di13 di2 di1 di0 a2 a1 a0 b3 b2 b1 b0 di cl ce t hd t su t ch t cl t el t es t lc t eh a3 do287 do286 do285 do2 do1 do0 a2 a1 a0 b3 b2 b1 b0 di do cl ce t el t es t ch t cl t su t hd t ddo
LC72711W, 72711lw no.6167-16/26 structure of the post-correction output data post-error correction data can be output by using ccb address #fb. although there are up to 288 bits of valid data that can be output, it is possible to stop clock input (cl input) and set ce to the low level, and output the remaining data on the next interrupt with no harmful effects whatsoever. ? the maximum amount of data that can be output is 288 bits (36 bytes), and the contents of the status register (stat) and the block number register (blno) are added as the first two bytes. ? the contents of the stat and blno registers are output lsb first. ? the post-correction data is output in order starting with the first bit in each single block of data. ? the bic code is not output. ? the values of the output data are not guaranteed if multiple data read operations are performed for a single interrupt signal (int). stat (8 bits) blno (8 bits) data section (176 bits) post-error correction data layer 2 crc (14 bits) parity (82 bits) do0 to do7 do8 to do15 do16 to do191 do192 to do205 do206 to do287 layer 4 crc check circuit the basic outline of this operation is the same as that described in the layer 4 crc detection circuit section earlier in this document. the data group data used for this error detection operation is sent to the ic using the ccb interface. the value #fc is used as the ccb address. the data group data is transferred in 8-bit units. there is no upper limit on the amount of data that can be transferred (the value n in the figure below), and the data transfer may be divided into multiple operations. register output the ic internal status and block number registers are special-purpose registers that can be read out by applications. (see the discussion of the read register data update timing on page 12.) the application inputs the ccb address #fd to di. the status register data is output first followed by the block number register data. a3 n n-1 n-2 cr2 cr1 cr0 a2 a1 a0 b3 b2 b1 b0 di cl ce crc4 pin output note: the number of items, n, refers to the number of 8-bit items. crc4 pin output after n items have been transferred. t crc t eh t es t el t ch t cl t hd t su a3 bln7 bln6 bln5 st2 st1 st0 a2 a1 a0 b3 b2 b1 b0 di do cl ce t su t hd t ch t cl t es t el t ddo
LC72711W, 72711lw no.6167-17/26 notes on operation during resets and in standby mode reset signal the reset operation is executed when the supply voltage (v dd ) rises above 3.4v (2.5v in the lc72711lw) and the rst pin input level is held at or below v il for 300ns or longer. (see the figure below.) when power is first applied, or when power is removed and applied again, always apply a reset before using this ic. pin states during reset low level:clk16 (5), data (6), flock (7), block (8), fck (9), bck (10) high level: int (33), rdy (16), crc4 (11), dreq (12) open: d0 (17) to d15 (32), do (36) reset operating range the states of the output pins as the result of a reset signal are stipulated in the "pin states during reset" item above. the ic internal flip-flops are all reset. while the shift registers used for delay are also reset, the memory array is not influenced by this operation. however, since memory is not refreshed, data cannot be retained. the crystal oscillator circuit is not stopped. post-reset data input after a reset operation has completed, if at least one clock cycle (about 278ns when the ic's main clock is 3.6mhz) elapses, the register write circuit will be functional. (that is, the ic can accept data.) notes on standby mode the ic is set to standby mode by applying a high level to the stnby pin. since all ic operations are stopped in this mode, the state is essentially equivalent to removing power from the ic. (note that after clearing standby mode, applications must wait the oscillator stabilization time before using the ic.) the pin output states during standby mode are the same as those states during a reset as described above. output conditions for post-error correction output (default mode) (1) for each block (272 bits) of received data, the ic applies (272, 190) code error correction and a layer 2 crc error check. after the error correction has completed, the ic prepares to transfer the data to the cpu and outputs an interrupt signal from the int pin. this is referred to as horizontal correction output. (2) note that under the default operating conditions, this interrupt signal is not output unless the corresponding output data meets the following three conditions. ? error correction completed correctly and no errors were discovered in the layer 2 crc check. ? the data was received in both block and frame synchronization. ? the data is packet data. (3) if the data could not be corrected in horizontal correction, product code correction is performed in frame units and a second horizontal correction operation is performed for this data that could not be corrected by the first horizontal correction. this sequence of operations is called vertical correction. the output conditions for data that can be acquired after vertical correction are as follows. ? the data that could not be corrected by horizontal correction only, but that was corrected by vertical correction. ? the data is packet data. continued on next page. rst vil(0.3v dd ) vih 300ns(min) v dd voltage 3.4v (2.5v in the lc72711lw)
LC72711W, 72711lw no.6167-18/26 continued from preceding page. this means that data that was fully corrected by horizontal correction is not output. also, packet data that could not be corrected by either horizontal correction or vertical correction is not output. furthermore, post-vertical correction parity packet data is also not output. (4) applications can clear the int signal selection conditions described in (2) and (3) above by setting bit 5 (int_move) in the control register. (5) vertical correction is performed when all of the packet data in a frame is received in frame synchronization and furthermore when it was not possible to correct all of the packet (block) data with horizontal correction. vertical correction is not performed if one frame of data with no errors was received or the receiver was not in frame synchronization during reception. to prevent incorrect correction, error correction using vertical correction is not performed for packets error correction using horizontal correction fully completed and for packets that had no errors. (6) under the default settings, if vertical correction is not performed, the corresponding post-vertical correction output is not output. applications can specify the post-vertical correction data to be output regardless of whether or not vertical correction is performed by setting bit 2 (vec_out) in control register 2. note 1. in this case, if data with absolutely no errors is received, completely identical data will be output twice, once as horizontal correction output, and once as vertical correction output. this status is identical to the output status of the lc72700e. note 2. immediately after power is applied, undefined data that is, in principle, not required by applications, will be output as post-vertical correction data. cpu interface basic limitations to save internal memory, this ic limits its output data buffer to the smallest size possible. since the data received by the ic is written to memory continuously without interruption, the post-correction data in the output data buffer that should be read out may be overwritten by the following data if readout of the data is delayed. the output timing for post-correction data, both horizontal and vertical, is stipulated as follows for this ic. (1) when the ic completes preparation of the output data, it drops the int pin to the low level as a transfer request. (2) during data output, there are periods when only horizontal data can be read out, and there are other periods when both horizontal data and vertical data can be read out in a time-division multiplexed manner. (3) applications must complete the data transfer operation within 9ms after the int pin goes low. if only post-horizontal correction data is output, the data transfer may be performed within an 18ms period. after the stipulated period, the next data will be written to the output buffer replacing the previous data, even if the cpu is reading out the data. (4) the amount of data that can be read for a single transfer request (int) for each of the horizontal and vertical data is one block only. the post-vertical correction data is output in order starting with block number 1 after vertical correction processing completes. the parity block data is not output. 18ms 68 s 68 s 1ms int horizontal data only output horizontal data output period horizontal data output period vertical data output period horizontal and vertical data output period during which data retention is not guaranteed figure 2 external interface - basic timing
LC72711W, 72711lw no.6167-19/26 notes on data output timing (relationship with the received data) figure 3 shows the timing relationship between the received data and the interrupt control signal (int). however, the delay from the actual received signal due to demodulation operations in msk demodulation blocks is ignored. block synchronization is established by discriminating the bic code. as shown in figure 3, the data for the nth packet can be output during reception of the following packet (number n+1). figure 4 shows the output timing for post-vertical correction data. in vertical correction, the data for a single frame is stored in memory and the correction operation is performed if frame synchronization was established and it was not possible to correct all the packet data in horizontal correction. the timing with which vertical correction is started is the start of the frame. horizontal correction is performed for each packet while packets 1 through 28 in the nth frame are being received, and this data is passed to the cpu interface. vertical correction is performed for the data from the previous frame (frame n-1) in the unused time periods during that processing. the vertical correction data consists of 190 blocks that are output, and this data is output at the rate of one block for every block received, in order starting at the time the 29th packet (block) is received. only data from the data blocks in the fm multiplex broadcast frame structure is output, and the last block (block 190) is output during reception of the 218th block. as indicated previously (page 17) packet data that was, for example, corrected completely by horizontal correction, is not output in the vertical correction output data. (the int signal is not issued.) however, the order in which the horizontal output is produced is not speeded up by the amount of the packet data that is not output. for example, if data packets 1 to 100 were corrected by horizontal correction, output of the post-vertical correction packet data for packet 101 will not occur at the reception position of block number 29 in figure 4, but at the reception position for packet data number 129. bic bic 18ms 300ns max 300ns max 62.5 s 68 s packet n-1 packet n+1 packet n data 1ms recieved data bck int data cannot be guaranteed packet n data output output period for packet n+1 data bck fck int 1ms output periods for post-vertical correction data from the previous frame. 9ms 9ms 62.5 s 18ms 18ms 271 recieved block signal 272 1 2 3 2 1 28 29 30 31 220 219 218 189 190 first frame nth frame 18ms ?
LC72711W, 72711lw no.6167-20/26 cpu connection example this section presents examples of the connection of this ic to a cpu. note that care is required with respect to read timing, since the time required to read a register, and the time required to read a post-correction data packet (22 bytes) are different. ? normal connection when hardware waits are applied to the cpu, the wait time (rdy width) requires care. buswd = low: 8 bits buswd = high: 16 bits ? dma transfer mode i/o read/write operations are used for the normal register read and write operations. however, programmable wait states may need to be inserted, depending on the execution speeds. dma processing is only used for readout of post-correction data. applications can select whether rd or dack is used as the dma read control signal by setting a register. the default is to use the rd signal. the data bus width in dma mode is always 8 bits. cpu dma mode setting example (for reference only) sh series: transfer type: 2-cycle transfer transfer mode: single transfer mode v series: address mode: dual address mode bus mode: cycle stealing mode the source side (the fm multiplex ic) address is fixed at 0. rst iocnt2 iocnt1 wait int cs rd wr wr rd cs int rdy dack dreq sp rst iocnt2 dreq int cs rd wr wr rd cs int rdy sp LC72711W, lc72711lw LC72711W, lc72711lw d0 to d7 (d0 to d15) a0 to a3 buswd bus-width 8bits port1 cpu port1 dack dreq dack bus-width 8bits cpu d0 to d7 a0 to a3 buswd iocnt1
LC72711W, 72711lw no.6167-21/26 ? data bus i/o control block the data bus (d0 to d15) can be controlled with two control signals: iocnt1 and iocnt2. these pins must be held low if unused. cpu connection example * sck, tx, and rx are the cpu serial interface channel. normally, i/o port pins may be used for these lines. * the resistance of the do pin pull-up resistor must be selected according to the transfer clock speed. int do sp iocnt1 cs iocnt2 rd dack control register 2 bits 1 and 2 d0 to d15 LC72711W, lc72711lw cpu a1/ce a0/cl a2/di rst port2 (int) port3 rx(*) tx(*) sck(*) port1
LC72711W, 72711lw no.6167-22/26 control program compatibility this ic allows the majority of the control software used to be compatible with sanyo?s other fm multiplex ics, in particular, the lc72700e, lc72705e, lc72706e, lc72708e, and lc72709e(w). however, the following aspects of the control software require modification. ? values of the register addresses the addresses of the allowable bic error count, synchronization error protection count, control registers, the layer 4 crc register, and other registers have been modified. the ccb address for serial i/o over a ccb bus has not been changed. ? int signal output timing the int signal output timing for data output is as follows. a circle ("o") indicates that int is output, and a cross ("x") indicates that the signal is not output. control control horizontal correction output vertical correction output item register 1 register 2 operational overview correct incorrect correct bit 5, bit 2, data data parity data ng int_move vec_out default value l h operation identical to that of the lc72705/06/07e ?? ? ??? ??? ?? ?
LC72711W, 72711lw no.6167-23/26 sample data acquisition flowchart note: the figure below is for allocation of received data at the layer 3 level. this documentation is present as an example for reference purposes only of fm multiplex data acquisition processing by the system cpu. its operation is not guaranteed. int end status acquisition correction complete? synchronized? was this post-horizontal correction data? prefix discrimination prefix discrimination is the data group complete? is the data group complete? is the decoding identifier 1? start decoding and presentation processing layer 4 crc check start decoding and presentation processing layer 4 crc check yes yes yes yes read in the postcorrection data (22 bytes) ** this discrimination is not required with the default settings. (no int signal is issued.)
LC72711W, 72711lw no.6167-24/26 additional notes in addition to the above processing, processing required for layer 3 (data group) level processing includes deletion of inappropriate data. although rare, in certain cases the ic will send inappropriate packet data that does not belong to any data group currently being broadcast. the following three points are possible reasons for this occurring. (1) the ic frame synchronization circuit generates an incorrect synchronization state, and the ic incorrectly outputs parity packet data as normal packet data. this can occur when the back protection count is less rigorous (2 or lower), or during weak field reception. (2) while extremely rare, incorrect correction can occur. (this almost never happens.) (3) noise entering the data transfer lines between the fmd ic and the cpu within the end product set. inappropriate packet data that occurs for these reasons and does not belong to any data group, will not be updated, and will remain in the program storage memory indefinitely. if the application does not include a routine that searches for and deletes inappropriate data, program storage memory will overflow at some point. also, applications should perform a layer 4 crc check after data group completion and before program display. prefix discrimination recend? update? end store in the corresponding data group storage area. check the correctness of the received data packet. update the data in the existing data storage area. allocate a storage area the size of the data group. yes yes no no yes yes is the data group complete? is this the data group for the first reception?
LC72711W, 72711lw no.6167-25/26 sample application circuit (ccb serial interface) 16pf 16pf rst 32 49 561 + + + + - - - - 64 1 10 f 16 331 5k ? do cpu interface stnby a2/di a1/ce a0/cl int sqfp-64 fm composit analoggnd 3.3 f (*) 22 h (*) 22 h (*) LC72711W, lc72711lw
LC72711W, 72711lw no.6167-26/26 ps ? the darc (data radio channel) fm multiplex broadcast technology was developed by nhk (japan broadcasting corporation). ? the darc is a registered trademark of nhk engineering services,inc. (nhk-es). ? a separate contract with nhk-es is required in advance for the manufacture and/ or sales of electronic equipment in japan and other countries that uses the patents, which are related to darc technology, and which are registered in japan and such other countries by nhk independently or in cooperation with a third party. ? darc and the logo shown on the right-hand side can be displayed on electronic equipment that uses darc technology by the conclusion of a contract with nhk-es. please contact nhk engineering services for further details. contact information: nhk engineering services,inc. phone: +81- (0)3-5494-2400 (main) url: http://www.nes.or.jp/index.html * notice the number of shipments of this lsi will be reported to nhk-es by sanyo semiconductor co., ltd (the number of samples is excluded). d ata radio channe l sanyo semiconductor co.,ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. this catalog provides information as of october, 2007. specifications and information herein are subject to change without notice.

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